High-Speed Column Level ADC Design of Full Parallel Two-Step Nested TDC for CMOS Image Sensor

This study presents a column-level analog-to-digital converter (ADC) designed specifically for CMOS image sensors. It is characterized by a two-phase fully parallel architecture combined with time-to-digital conversion (TDC) technology, resulting in high-speed performance. After the coarse-to-fine conversion process is completed, the output of the comparator is restricted by the clock signal. This results in the generation of a time difference value during the last clock cycle of the conversion. TDC is used to convert the difference into the corresponding numerical code and compare it with the ADC conversion results presented in this article. While realizing high-precision A/D conversion, the conversion speed of ADCs has greatly improved. The circuit proposed in this article is developed and validated based on 55 nm CMOS technology. In a design environment, the analog voltage is set at 3.3 V, the digital voltage at 1.2 V, and the input signal range at 1.5 V. The entire system operates at a clock speed of 100MHz. In this instance, the paper presents a 12-bit ADC that achieves an integral nonlinearity (INL) of +1.47/-1.74 LSB, a differential nonlinearity (DNL) of +0.8/-0.8 LSB, and a signal-to-noise ratio (SNDR) of 68.272 dB. The ADC main architecture designed in this paper adopts a fully parallel design that is not limited to a fixed design accuracy. It achieves a high parallel time multiplexing rate of up to 100% through an adaptive time multiplexing mechanism. Additionally, the ADC architecture includes a 3-bit time-to-digital converter, enhancing the efficiency of the analog-to-digital conversion process. The column ADC circuit presents an efficient ADC design solution that is well-suited for high frame rates and large-area array CMOS image sensors.