Sub-Harmonic Stability and Slope Compensation Boundary in Peak/Valley DC–DC Converters

Sub-harmonic oscillations are a key stability concern in fast-switched inductor power supplies using clocked constant-period peak/valley-current loops. Using generalized models, IC designers can predict and suppress sub-harmonic oscillations with minimal overhead. This work presents an insightful, generalized, and comprehensive time-domain analysis of sub-harmonic oscillation propagation and suppression via slope compensation in constant-period peak/valley-current control. Since it is unstated and unvalidated in the literature, an exact, easy-to-apply expression for the slope compensation boundary is derived in terms of basic circuit operating parameters, showing that it is half of the difference in the drain and energize slopes in peak mode, and half of the difference in the energize and drain slopes in valley mode, lying beyond the conventionally accepted half drain (peak) and energize (valley) slope criteria. The prior literature also does not account for the impact of parasitic resistances on the duty-cycle-based stability boundary beyond which sub-harmonic oscillations begin. We address these gaps and establish a theoretical basis for the absence of sub-harmonic oscillations in DCM. Additionally, existing approaches to slope selection ensure stability but do not target the rate of suppression. We address this by proposing a compensation slope that achieves 90% suppression of the initial imbalance within three switching periods.