Back-illuminated SPAD with 89.4% peak PDP at 660 nm based on 40 nm CIS technology

A silicon single-photon avalanche diode (SPAD) fabricated in a 40 nm CMOS image sensor (CIS) technology is reported. An N-well/deep P-well (DPW) structure on a CIS epitaxial wafer is employed, where the N-well and lightly doped epitaxial layer form a virtual guard ring that suppresses edge breakdown. The device exhibits a breakdown voltage of 22.7 V, a peak photon detection probability (PDP) of 89.4% at 660 nm and 3 V excess bias voltage, and a median dark count rate (DCR) of 0.6 cps/µm². A timing jitter of 144 ps full width at half maximum and an afterpulsing probability below 0.3% are achieved. Temperature-dependent measurements show a pronounced PDP redshift at 60 °C, accompanied by enhanced peak and long-wavelength PDP. The SPAD is suitable for high-performance low-light visible imaging applications.