Accelerating FAEST Signatures on ARM: NEON SIMD AES and Parallel VOLE Optimization

FAEST is a National Institute of Standards and Technology post-quantum signature candidate based on the Vector Oblivious Linear Evaluation-in-the-Head paradigm, whose signing performance is dominated by repeated Advanced Encryption Standard Counter-based Pseudorandom Generator calls. The reference implementation provides no FAEST-specialized acceleration for Advanced RISC Machine platforms. This paper proposes a three-layer Advanced Reduced Instruction Set Computer Machine NEON Single Instruction Multiple Data optimization: a register-resident 256-byte S-box with Table Lookup/Table Lookup with Extension-based SubBytes and four-way/eight-way parallel Advanced Encryption Standard processing; a fixed-length Pseudorandom Generator specialized for the FAEST tree structure; and Portable Operating System Interface for Unix thread-based parallelization of independent Vector Oblivious Linear Evaluation instances. Evaluated on all 12 parameter sets of FAEST v2 on Raspberry Pi 4 (without Advanced Reduced Instruction Set Computer Machine version 8 crypto-extensions) and Apple M2 (with hardware Advanced Encryption Standard support), the proposed method achieves signing speedups of up to 136.9x on Raspberry Pi 4 and 330.1x on Apple M2 over the pure-C reference. On Raspberry Pi 4, the NEON implementation outperforms OpenSSL; on Apple M2, the NEON-plus-Portable Operating System Interface for Unix thread configuration outperforms hardware-accelerated OpenSSL across all parameters, confirming that NEON SIMD combined with task-level parallelization can exceed hardware-accelerated single-thread throughput on Advanced Reduced Instruction Set Computer Machine-based platforms.