ParSCo: Performance-Driven <u>Par</u> titioning and <u>S</u> cheduling <u>Co</u> -optimization Framework for Processor-based Emulation

As the scale and complexity of designs increase, functional verification becomes a critical part of the very-large-scale integration (VLSI) design flow. However, existing processor-based emulation systems suffer from inefficiencies due to the misalignment objective between partitioning and scheduling, which are traditionally treated as separate and independent stages during compilation. To address this issue, we propose ParSCo , a partitioning and scheduling co-optimization framework that explicitly aligns the objectives of both stages by jointly considering cut minimization and topological order balancing (TOB) under multiple constraints. To integrate these objectives and constraints into our framework, we incorporate them into all partitioning and scheduling stages and further develop a set of novel techniques, including TOB-aware coarsening with multiple constraints , global growing initial partitioning with fixed nodes , TopoRefinement , and partitioning-aware scheduling , which collectively enhance the co-optimization process in emulation compilation. Furthermore, we establish theorems that reduce the time complexity of gain calculation and update to O (1), significantly improving the computational efficiency of the whole process. Furthermore, we evaluate the proposed method on the public and open-source chip design benchmarks, which have up to nearly 10 million cells. ParSCo significantly extends ideas and algorithms that first appeared in our previous work TopoOrderPart and achieves a 15% improvement. Extensive experimental results demonstrate the effectiveness of ParSCo , achieving an average improvement of 22.5% in time step reduction, 72% enhancement in TOB, and 55% acceleration in CPU time compared to the state-of-the-art (SOTA) two-stage partitioning and scheduling approach.