Corrigendum: A data-centric chip design agent framework for Verilog code generation
This is a corrigendum for the article “A data-centric chip design agent framework for Verilog code generation” published in ACM Trans. Des. Autom. Electron Syst. 30, 6, Article 93 (October 2025), 27 pages.
Authors
- Zhuoliang Zhao (ORCID: https://orcid.org/0000-0001-6252-2160)
- Cangyuan Li (ORCID: https://orcid.org/0000-0002-7193-464X)
- Shengwen Liang (ORCID: https://orcid.org/0000-0001-8407-2594)
- Ying Wang (ORCID: https://orcid.org/0000-0001-5172-4736)
- Mengdi Wang (ORCID: https://orcid.org/0000-0002-7012-2308)
- Huawei Li (ORCID: https://orcid.org/0000-0001-8082-4218)
- Yinhe Han (ORCID: https://orcid.org/0000-0001-5113-8067)
- Zhirong Chen (ORCID: https://orcid.org/0009-0001-7039-7707)
- Xinyang He
- H. M. Yan
- Wenlong Zhu (ORCID: https://orcid.org/0009-0002-9237-559X)
- Yunhao Zhou (ORCID: https://orcid.org/0000-0002-5158-7417)
- Yuan Cheng (ORCID: https://orcid.org/0009-0001-7591-0418)
- Dantong Jin (ORCID: https://orcid.org/0009-0001-9107-8764)
- Xiaowei Li (ORCID: https://orcid.org/0000-0002-0874-814X)
Institutions
- Shanghai University (CN)
- Chinese Academy of Sciences (CN)
- Institute of Computing Technology (CN)
- Zhejiang Lab (CN)
- Chengdu Institute of Biology (CN)
- University of Chinese Academy of Sciences (CN)
- Nanjing University (CN)
Publication Details
- Journal
- ACM Transactions on Design Automation of Electronic Systems
- Published
- 2026-04-11
- DOI
- https://doi.org/10.1145/3802988
- Primary Topic
- Low-power high-performance VLSI design
- Type
- article
- Field-Weighted Citation Impact
- 0.00