TopoGeoNet: A Heterogeneous Model for End-to-End Congestion Prediction and Optimization in FPGA Placement

Recent approaches to congestion prediction and routability-driven placement have made progress, yet important limitations remain. Most existing models rely on heuristic-based intermediate features (e.g., RUDY, pin density) rather than fully end-to-end learning, and many capture either netlist topology or geometric placement context, but not both, limiting their performance. Moreover, when model gradients are used to guide placers, they are often propagated through such intermediate features, reducing their accuracy and effectiveness. To address these gaps, we propose TopoGeoNet , a heterogeneous neural network that unifies graph-based message passing with convolutional U-Net processing over spatial grids. Through bi-directional node–grid communication, TopoGeoNet jointly leverages netlist topology and geometric placement information for accurate congestion prediction. Trained on ISPD’2016 FPGA benchmarks, TopoGeoNet achieves an 8.3% improvement in prediction accuracy over state-of-the-art ML baselines. When integrated into a routability-driven FPGA placer, it improves congestion scores by 16% on average and reduces total place-and-route runtime by 5% without degrading routed wirelength. Compared with state-of-the-art ML prediction models that provide inference and gradients through intermediate features, TopoGeoNet delivers superior routability results, highlighting the advantages of fully end-to-end prediction and differentiability.

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Publication Details

Journal
ACM Transactions on Design Automation of Electronic Systems
Published
2026-04-10
DOI
https://doi.org/10.1145/3808232
Primary Topic
VLSI and FPGA Design Techniques
Type
article
Field-Weighted Citation Impact
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article

TopoGeoNet: A Heterogeneous Model for End-to-End Congestion Prediction and Optimization in FPGA Placement

Zhishang Luo, David Z. Pan, Rachel Selina Rajarathnam, Yusu Wang et al.
ACM Transactions on Design Automation of Electronic Systems
VLSI and FPGA Design Techniques
article

TopoGeoNet: A Heterogeneous Model for End-to-End Congestion Prediction and Optimization in FPGA Placement

Zhishang Luo, David Z. Pan, Rachel Selina Rajarathnam, Yusu Wang, Zhili Xiong
article en

Abstract

Recent approaches to congestion prediction and routability-driven placement have made progress, yet important limitations remain. Most existing models rely on heuristic-based intermediate features (e.g., RUDY, pin density) rather than fully end-to-end learning, and many capture either netlist topology or geometric placement context, but not both, limiting their performance. Moreover, when model gradients are used to guide placers, they are often propagated through such intermediate features, reducing their accuracy and effectiveness. To address these gaps, we propose TopoGeoNet , a heterogeneous neural network that unifies graph-based message passing with convolutional U-Net processing over spatial grids. Through bi-directional node–grid communication, TopoGeoNet jointly leverages netlist topology and geometric placement information for accurate congestion prediction. Trained on ISPD’2016 FPGA benchmarks, TopoGeoNet achieves an 8.3% improvement in prediction accuracy over state-of-the-art ML baselines. When integrated into a routability-driven FPGA placer, it improves congestion scores by 16% on average and reduces total place-and-route runtime by 5% without degrading routed wirelength. Compared with state-of-the-art ML prediction models that provide inference and gradients through intermediate features, TopoGeoNet delivers superior routability results, highlighting the advantages of fully end-to-end prediction and differentiability.

ACM Transactions on Design Automation of Electronic Systems
University of California San Diego (US), The University of Texas at Austin (US)
Openalex Percentile: Top 21%
VLSI and FPGA Design Techniques
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