<scp>HMC</scp> ‐ <scp>DSR</scp> : An <scp>FPGA</scp> ‐Accelerated Clustered Routing Protocol for Scalable and Energy‐Efficient <scp>MANETs</scp>

ABSTRACT Mobile Ad hoc Networks (MANETs) are dynamic, infrastructure‐less systems used in applications requiring rapid deployment and decentralized communication, such as military, emergency, and IoT systems. Traditional protocols, such as dynamic source routing (DSR), face significant limitations in these environments due to high latency, scalability challenges, and excessive control overhead. This study presents a novel homogeneous clustered dynamic source routing (HMC‐DSR) protocol implemented using field‐programmable gate array (FPGA) technology to enable energy‐efficient, low‐latency, and real‐time routing in MANETs. The protocol partitions the network into homogeneous clusters and embeds cluster‐aware logic into routing packets, enabling localized decision‐making. The routing protocol is synthesized and realized on a Virtex‐5 FPGA, achieving real‐time processing at 256 MHz. Simulation results demonstrate a 20.7% reduction in end‐to‐end delay (E2ED), 15.8% lower power consumption, and significant improvements in hardware resource utilization, including a 30.2% reduction in flip‐flop and 27.4% in slice utilization. The packet delivery ratio (PDR) remains near‐perfect under various mobility scenarios. The originality of this work lies in integrating clustering techniques with reconfigurable hardware acceleration, bridging the gap between software protocol design and real‐time embedded implementation. The HMC‐DSR protocol provides a scalable and efficient routing framework suitable for latency‐sensitive, energy‐constrained environments, setting the stage for future security and AI‐based adaptive routing extensions.