Investigation of temperature-dependent oxide capacitance in paraelectric monoclinic doped HfO2/SiO2 gate stacks implemented on 4H-SiC

Doped, monoclinic HfO2 exhibits the paraelectric property of decreasing dielectric constant with increasing temperature. If utilized as the gate oxide of a metal–oxide–semiconductor field-effect transistor, this effect could enable a self-limiting reduction in current passing through the device during intermittent faults like short circuits. This study fabricates gate stacks comprising 30 nm doped HfO2 layers, on a 6 nm SiO2 interlayer, deposited via atomic layer deposition onto 4H-SiC epitaxial wafers to form MOS capacitors (MOSCAPs). Different dopant types (Al and Si) and ratios for doped HfO2 are investigated, with annealing temperatures ranging from 900 to 1100 °C. X-ray diffraction analysis confirms that all the annealed chips are predominantly monoclinic, and the unannealed chips amorphous. Electrical measurements assess the viability of the layers according to conventional SiC-oxide metrics such as flatband voltage, hysteresis, interface state density (DIT), and gate leakage current (IL), while also considering the change in accumulation gate capacitance (ΔCOX) against temperature. The most promising results came from MOSCAPs using a doped HfO2 layer using a 1:19 Al2O3:HfO2 deposition ratio, annealed at 1100 °C in N2. This combination yielded the lowest average DIT of 5.47 × 1011 eV−1 cm−2, and a ΔCOX of −19% between room temperature and 523 K. However, the drawback was the high IL observed in all 1100 °C annealed layers. Scanning electron microscopy indicated the large crystal grain boundaries on the HfO2 surface during annealing to be the probable cause of the gate leakage. Unannealed amorphous chips offer lower IL but sacrificed performance across other crucial electrical and ΔCOX parameters.