DART: A Lock-free Two-layer Hashed ART Index for Disaggregated Memory

Disaggregated memory architecture decouples computing and memory resources into separate pools connected via high-speed interconnect technologies, offering substantial advantages in scalability and resource utilization. However, this architecture also poses unique challenges in designing effective index structures and concurrency protocols due to increased remote memory access overhead and its shared-everything nature. In this paper, we present DART, a lock-free two-layer hashed Adaptive Radix Tree (ART) designed to minimize remote memory access while ensuring high concurrency and crash consistency in the disaggregated memory architecture. DART incorporates a hash-based Express Skip Table at its upper layer, which reduces the round trips of remote memory access during index traversal. In the base layer, DART employs an Adaptive Hashed Layout within ART nodes, confining remote memory accesses during in-node searches to small hash buckets. By further leveraging Decoupled Metadata Organization, DART achieves lock-free atomic updates, enabling high scalability and ensuring crash consistency. Our evaluation demonstrates that DART outperforms state-of-the-art counterparts by up to 5.8× in YCSB workloads.

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Publication Details

Journal
Proceedings of the ACM on Management of Data
Published
2026-04-02
DOI
https://doi.org/10.1145/3786636
Primary Topic
Parallel Computing and Optimization Techniques
Type
article
Field-Weighted Citation Impact
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article

DART: A Lock-free Two-layer Hashed ART Index for Disaggregated Memory

Shengan Zheng, Linpeng Huang, Zhenlin Qi, Jianguo Wang et al.
Proceedings of the ACM on Management of Data
Parallel Computing and Optimization Techniques
article

DART: A Lock-free Two-layer Hashed ART Index for Disaggregated Memory

Shengan Zheng, Linpeng Huang, Zhenlin Qi, Jianguo Wang, Hong Mei
article en

Abstract

Disaggregated memory architecture decouples computing and memory resources into separate pools connected via high-speed interconnect technologies, offering substantial advantages in scalability and resource utilization. However, this architecture also poses unique challenges in designing effective index structures and concurrency protocols due to increased remote memory access overhead and its shared-everything nature. In this paper, we present DART, a lock-free two-layer hashed Adaptive Radix Tree (ART) designed to minimize remote memory access while ensuring high concurrency and crash consistency in the disaggregated memory architecture. DART incorporates a hash-based Express Skip Table at its upper layer, which reduces the round trips of remote memory access during index traversal. In the base layer, DART employs an Adaptive Hashed Layout within ART nodes, confining remote memory accesses during in-node searches to small hash buckets. By further leveraging Decoupled Metadata Organization, DART achieves lock-free atomic updates, enabling high scalability and ensuring crash consistency. Our evaluation demonstrates that DART outperforms state-of-the-art counterparts by up to 5.8× in YCSB workloads.

Proceedings of the ACM on Management of DataVol. 4(1)
Shanghai Jiao Tong University (CN), Peking University (CN), Purdue University West Lafayette (US)
Openalex Percentile: Top 22%
Parallel Computing and Optimization Techniques
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