Characterization of Electronic Stress-Induced Changes in Multilayer MoS ₂

overlap with electrodes, channel area, contact length) on 50 test structures across five chips to move beyond anecdotal conclusions. We found no universal correlations before DC stress. However, device-level geometry was correlated with I-V behavior after DC stress, suggesting that electrode contacts play a more dominant role than morphology in determining performance. Delamination and thinning induced by DC stress led to localized reductions in charge carrier density within the affected regions. Further, delamination and thinning appear to map to I-V device performance in a few samples, but the correlation is lost when a larger sample size is considered. This suggests significant sample-to-sample variability in surface electronic states of the test structures. We also discuss how environmental factors introduced during fabrication may contribute to the observed heterogeneous device response. Progress will require high-resolution, multimodal analysis across many samples constructed under controlled, clean conditions. By building data sets that capture variability, we can better identify the true drivers of performance.