Temperature influence on the electrical performance of symmetric high-k spacer underlap InGaAs nanotube field-effect transistor

• The study investigates temperature effects on symmetric high-k spacer underlap InGaAs Nanotube FETs, revealing performance trends across extreme conditions. • On-current, threshold voltage, and subthreshold slope exhibit strong temperature dependence, highlighting critical thermal challenges in nanoscale transistor design. • TiO₂ and HfO₂ spacers enhance electrostatic control, reduce leakage, and slow thermal degradation, improving transistor reliability and scalability. • Temperature-driven capacitance variation significantly impacts fT and fMAX, degrading RF performance while cryogenic operation enhances device metrics. • The proposed underlap design supports thermally robust, energy-efficient, and high-speed nanoelectronics, enabling future RF and low-power circuit applications. This work presents a comprehensive temperature-dependent investigation of symmetric high-k spacer source/drain underlap Indium Gallium Arsenide (InGaAs) nanotube field-effect transistors (NT-FETs) over a wide thermal range from –73 °C to 177 °C. Three-dimensional TCAD simulations are employed to analyze static, analog, and RF performance variations with temperature, incorporating quantum confinement, field-dependent mobility, and recombination effects. Results show that lowering the temperature to –73 °C enhances the on-state current by approximately 2× compared to 177 °C due to reduced phonon scattering and improved carrier mobility. The subthreshold swing improves by nearly 54%, indicating superior electrostatic control at low temperatures. RF performance metrics, including cut-off frequency (fT), maximum oscillation frequency (fMAX), intrinsic delay, and parasitic capacitances, exhibit strong temperature dependence, with maximum gains observed in the cryogenic and room-temperature regimes. A comparative assessment of multiple high-k spacer materials (Si₃N₄, Al₂O₃, Y₂O₃, HfO₂, and TiO₂) reveals that TiO₂ (k ≈ 40) provides optimal electrostatic stability and mitigates temperature-induced degradation by suppressing short-channel effects and threshold voltage variability. The study elucidates the physical mechanisms governing temperature sensitivity in InGaAs NT-FETs and demonstrates that symmetric high-k spacer underlap architectures significantly enhance thermal robustness, making them promising candidates for next-generation high-speed, low-power, and RF electronics operating under diverse thermal environments.