Effects of electron irradiation and thermal cycling on electrical properties of GaN HEMT

Purpose GaN HEMT devices are often exposed to harsh environments (such as irradiation and temperature fluctuations) in practical applications, which can significantly degrade their reliability. The purpose of this study is to investigate the degradation of electrical performance and failure mechanisms of GaN HEMT devices under the combined effects of electron irradiation and thermal cycling, providing valuable reference information for the reliability assessment of GaN HEMT devices. Design/methodology/approach By comparing with the individual thermal cycling experiments, this study investigates the effects of the combined electron irradiation and thermal cycling on device failure. An optical microscope was used to observe the liftoff phenomenon of the bond pads, and finite element analysis was used to simulate the device’s behavior. In addition, G4 simulation software was used to analyze the accumulation of residual stress in the bond pad region after irradiation. These findings provide crucial insights into the failure mechanisms of the device under the combined effects of electron irradiation and thermal cycling. Findings Studies have shown that the electron irradiation on the device surface generated localized heat after the introduction of irradiation, which further led to residual stresses in the metal pad region. Under the combined effect of electron irradiation and thermal cycle, the device showed chip-level degradation in the first 750 thermal cycles, and the on-resistance increased by 20%. With the further extension of the aging time, the device entered the package-level degradation stage, and the on-resistance increases significantly, reaching 106 %. Originality/value This study provides valuable insights into the long-term reliability of P-GaN gate HEMTs for simulated space applications. By considering electron irradiation and thermal cycling as combined stress factors, the degradation process of the chip was examined, with initial degradation occurring at the chip level, followed by packaging-level degradation.