Scalable Reconfigurable Circuits with Double-Gate MoS <sub>2</sub> Transistors
double-gate transistors (DGFETs), which is compatible with conventional integration processes, enabling large-scale fabrication. A 10 × 10 array was successfully demonstrated─representing the largest array to date in the field of two-dimensional reconfigurable transistors for logic. By utilizing double-gate tuning combined with the resistive voltage division mechanism of the inverter, the unit achieves four distinct logic functions using only an n-type channel, while maintaining complete matching of input and output voltage range. Furthermore, we fabricated reconfigurable circuits with XOR/XNOR function through cascaded connections and demonstrated real-time switching between half-subtractor and comparator operations, thereby fully showcasing the unit's potential of cascading. This work provides a viable and practical approach toward the scalable integration of reconfigurable transistors.
Authors
- Hongyun Zhao (ORCID: https://orcid.org/0000-0002-1251-3888)
- Kuanglei Chen
- Jiankun Xiao
- Xun Zhang (ORCID: https://orcid.org/0000-0003-3586-9921)
- Jianhua Zhang (ORCID: https://orcid.org/0000-0001-7844-6035)
- Yu Geng
- Jinsen Shang
- Weiheng You
- Xiaoyu He
- He Jiang
- Zheng Zhang
Institutions
- Future Earth (CA)
- Advanced Materials and Devices (United States) (US)
- University of Science and Technology Beijing (CN)
Publication Details
- Journal
- ACS Nano
- Published
- 2026-04-02
- DOI
- https://doi.org/10.1021/acsnano.6c02873
- Primary Topic
- Low-power high-performance VLSI design
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China
- Ministry of Education of the People's Republic of China
- National Key Research and Development Program of China
- Fundamental Research Funds for the Central Universities