Storage I/O Characterization for an Embedded Multi-Sensor Platform: Performance Bottlenecks and Design Guidelines

Microcontroller-based embedded systems integrating multiple sensors are increasingly required to support continuous data acquisition, on-board processing, and long-term storage within tightly coupled hardware–software architectures. In such platforms, overall performance is often constrained not by computational capability but by storage I/O behavior, particularly under real-time constraints and concurrent workloads. This study presents a comprehensive empirical evaluation of eMMC storage performance on an STM32U5 microcontroller running the ThreadX RTOS. The proposed methodology combines multi-dimensional stress testing, controlled task concurrency (0–4 tasks), and long-duration aging analysis (90 h), together with timing variability assessment under electrical stress and interrupt-driven preemption. Both synthetic workloads and realistic sensor-node scenarios with heterogeneous and asynchronous access patterns are considered. The results highlight significant performance limitations, including up to 98% throughput degradation under four concurrent tasks and a nonlinear increase in metadata latency as free space decreases below 40% (from 10 ms to over 200 ms for file creation). Additionally, timing jitter increases by 2–5× under voltage variation and interrupt load. Based on these findings, practical firmware-level design guidelines are derived, including sector-aligned buffering, dedicated I/O task architectures, and proactive capacity management, enabling substantial improvements in throughput and latency. This study provides quantitative insights and reproducible methodologies for optimizing storage subsystems in multi-sensor embedded applications.