Near-Optimal PCM Wear Leveling Under AdversarialAttacks

Phase-change memory (PCM) is a promising memory technology known for its speed, high density, and durability. However, despite these advantages, a key challenge limiting PCM's widespread adoption is its finite endurance: each cell supports only a limited number of writes before becoming unreliable, and the failure of a single cell can compromise the entire device. This vulnerability makes PCM particularly susceptible to adversarial attacks that induce excessive writes to accelerate device failure. Wear-leveling mechanisms, which aim to distribute write operations evenly across PCM cells, are among the most widely used techniques to mitigate the limited endurance of PCM. However, while PCM wear leveling has been extensively studied in the systems and architecture communities, this problem remains largely unexplored from a theoretical perspective. We bridge this gap by presenting a novel algorithm that leverages hardware feedback to optimize PCM performance. We prove that our algorithm achieves nearoptimal worst-case guarantees and outperforms state-of-theart practical solutions both theoretically and empirically, providing an efficient approach to prolonging PCM lifespan.