A high-throughput, low-power module for on-chip packet sorting in large-area pixel detectors

Abstract Modern pixel detectors for high-energy physics require real-time, low-power packet sorting to manage extreme data rates and high hit-rate densities under tight area and power constraints. Unlike frame-based readout chips, which output all pixel data at fixed intervals, data-driven architectures send out only active pixel hits, enabling higher efficiency but producing unsorted, variable-latency data streams. We present a 28nm SRAM-based sorting module that uses simplified bucket sorting to group packets by event timestamp, reducing processing overhead and bandwidth. The radiation-hardened design achieves <5% data loss due to sorting, processes in parallel up to 60 consecutive events at 320 MHz, while sustaining 100 Gbit s -1 output data-rates and consuming less than 200 mW, to meet the requirements for integration in an upcoming hybrid pixel readout chip.