Verolig-A Code for Josephson Field-Effect Transistor Modeling.

The Verilog-A implementation corresponding to the gate-dependent compact model of the $L_g = 350$~nm device discussed in Sec.~III of the journal article Device Models for Josephson Field-Effect Transistors and for Superconducting Integrated Circuits. This article was submitted to the IEEE Journal of the Electron Devices Society and is still under review. // ============================================================================// Graphene Josephson FET (JoFET) Verilog-A Model// ----------------------------------------------------------------------------// Description:// Compact Verilog-A model of a graphene-based Josephson field-effect transistor// (JoFET) based on an RCSJ formulation with gate-tunable resistance and// critical current.//// ----------------------------------------------------------------------------// Usage in ADS://// - This model is intended to be used in Keysight ADS.// - Create a symbol from this Verilog-A module.// - Ensure the symbol is properly linked to this .va file.// - The symbol should expose three terminals: d (drain), s (source), g (gate).//// Recommended simulation setup:// * Gate (g): connect to a voltage source (Vg bias)// * Drain–Source (d–s): connect to a current source for current sweep// * Use transient simulation to observe device behavior//// ----------------------------------------------------------------------------// Notes://// - Designed primarily for transient simulations.// - Phase dynamics implemented using time integration (idt).//// - Optional small conductance is included across d–s for numerical convergence:// I(d, s) <+ gmin * V(d, s)// This helps avoid convergence issues in ADS. It can be reduced or removed// if not required, depending on simulation stability.//// - If discipline/nature definitions are already provided by the simulator// environment (e.g., via "disciplines.vams"), any duplicate header// Declarations should be removed to avoid redefinition errors.// Parameter Notes:// mu : carrier mobility (m^2/Vs)// nr : residual carrier density (m^-2)// Rc : contact resistance (Ohm)// alpha : scaling factor for Ic// Delta_ind : induced superconducting gap (J)// ----------------------------------------------------------------------------// ============================================================================

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Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-03-31
DOI
https://doi.org/10.5281/zenodo.19068550
Primary Topic
Advanced Electrical Measurement Techniques
Type
article
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article

Verolig-A Code for Josephson Field-Effect Transistor Modeling.

Jussi Ryynänen, Klaara Viisanen, Markus Lehtisalo, Kari Stadius et al.
Zenodo (CERN European Organization for Nuclear Research)
Advanced Electrical Measurement Techniques
article

Verolig-A Code for Josephson Field-Effect Transistor Modeling.

Jussi Ryynänen, Klaara Viisanen, Markus Lehtisalo, Kari Stadius, Heorhii Bohuslavskyi, Andrey Generalov, Shanuka Gamaethige
article en

Abstract

The Verilog-A implementation corresponding to the gate-dependent compact model of the $L_g = 350$~nm device discussed in Sec.~III of the journal article Device Models for Josephson Field-Effect Transistors and for Superconducting Integrated Circuits. This article was submitted to the IEEE Journal of the Electron Devices Society and is still under review. // ============================================================================// Graphene Josephson FET (JoFET) Verilog-A Model// ----------------------------------------------------------------------------// Description:// Compact Verilog-A model of a graphene-based Josephson field-effect transistor// (JoFET) based on an RCSJ formulation with gate-tunable resistance and// critical current.//// ----------------------------------------------------------------------------// Usage in ADS://// - This model is intended to be used in Keysight ADS.// - Create a symbol from this Verilog-A module.// - Ensure the symbol is properly linked to this .va file.// - The symbol should expose three terminals: d (drain), s (source), g (gate).//// Recommended simulation setup:// * Gate (g): connect to a voltage source (Vg bias)// * Drain–Source (d–s): connect to a current source for current sweep// * Use transient simulation to observe device behavior//// ----------------------------------------------------------------------------// Notes://// - Designed primarily for transient simulations.// - Phase dynamics implemented using time integration (idt).//// - Optional small conductance is included across d–s for numerical convergence:// I(d, s) <+ gmin * V(d, s)// This helps avoid convergence issues in ADS. It can be reduced or removed// if not required, depending on simulation stability.//// - If discipline/nature definitions are already provided by the simulator// environment (e.g., via "disciplines.vams"), any duplicate header// Declarations should be removed to avoid redefinition errors.// Parameter Notes:// mu : carrier mobility (m^2/Vs)// nr : residual carrier density (m^-2)// Rc : contact resistance (Ohm)// alpha : scaling factor for Ic// Delta_ind : induced superconducting gap (J)// ----------------------------------------------------------------------------// ============================================================================

Zenodo (CERN European Organization for Nuclear Research)
VTT Technical Research Centre of Finland (FI), Aalto University (FI)
Openalex Percentile: Top 26%
Advanced Electrical Measurement Techniques
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