Impact of Fabrication Defects on FPGA Logic Using Memristor-Based Memory Cells

Memristor-based configuration memory offers an alternative solution to the volatility and large area overhead of conventional Static Random Access Memory (SRAM)-based FPGA configuration memory. Their non-volatile nature and the possibility of stacking them on top of the logic layer in a process called Back-End-Of-Line (BEOL) manufacturing help not only dramatically reduce area consumption but also significantly reduce startup time. However, due to the comparatively high defect probability caused by manufacturing defects, traditional approaches for defect tolerance are not fit to address these defects. This work introduces an approach to defect-aware and tolerant synthesis. Based on this, an investigation into the defect tolerance of different architecture choices regarding the size of LUTs and the fracturability of LUTs is presented. We can show that smaller, non-fracturable LUTs exhibit a higher defect tolerance. Moreover, multiple strategies to improve the mapping result based on the properties of the logic functions are introduced. Notably, reducing the mapping complexity of logic clusters during the packing stage significantly improves the mapping success rate.