Physical design of a 32-bit RISC-V based microprocessor: A proof of concept for chaotic systems implementation

This work presents the physical design of a 32-bit RISC-V-based microprocessor ( μ P) as a proof-of-concept platform for implementing chaotic systems. The proposed μ P is derived from a subset of the 32-bit RISC-V integer ISA and adopts a Harvard architecture with separate instruction and data memories. It incorporates a UART-DMA bootloader that receives and stores instruction sequences in memory without processor intervention, accelerating program loading and reducing internal memory usage. The design also features a custom interrupt workflow enabling prioritized event handling and flexible peripheral integration. The μ P was described in Verilog-HDL and validated using Universal Verification Methodology (UVM); FPGA prototyping on a Nexys-4 DDR board further corroborated correct instruction execution and peripheral interaction using the Lorenz chaotic system as a representative workload. The complete physical design flow from RTL synthesis to GDSII layout generation was performed using Cadence tools (Genus, Innovus, and Virtuoso), resulting in a layout free of design-rule-check (DRC) and layout versus schematic (LVS) violations. • A 32-bit RISC-V microprocessor with integrated peripherals is implemented. • The design is based on the RVI32 ISA and integrates a Harvard architecture. • Experimental hardware results demonstrate stable chaotic behavior. • A complete ASIC design flow is demonstrated from RTL synthesis to GDSII generation.