A charge-trench-optimized SOI LDMOS low-power switch device

A novel charge trench SOI LDMOS device is proposed to enhance the breakdown voltage (BV) while maintaining reasonable specific on-resistance (Ron, sp). The structure introduces a dielectric charge trench between the top silicon layer and the buried oxide layer, which modulates the lateral electric field in the drift region and enhances the electric field of the buried oxide layer based on the Enhanced Dielectric layer Field (ENDIF) theory. Simulation results demonstrate that the optimized charge trench structure achieves a breakdown voltage of 281 V, representing a 30% improvement compared to the conventional SOI structure (215 V). The specific on-resistance increases from 12 mΩ cm 2 to 35 mΩ cm 2 . The Baliga figure of merit (FOM = BV 2 / Ron, sp) reaches 2.26 MW/cm 2 for the proposed structure versus 3.86 MW/cm 2 for the conventional structure. Sensitivity analysis reveals that trench height is the dominant parameter affecting device performance, followed by trench spacing and width. This work provides valuable design guidelines for high-voltage SOI power devices.