Statistical Performance Analysis Framework for Bundled‐Data Asynchronous Circuits With Dynamic Voltage Scaling

As the demand for low‐power electronic products grows, asynchronous circuits are considered a good alternative for addressing power consumption issues. Applying dynamic voltage scaling (DVS) in asynchronous circuits can further improve their power efficiency. However, asynchronous circuits face challenges, such as performance analysis considering voltage, temperature, and process variations. This paper proposes a new statistical performance analysis model for asynchronous pipelines. This model can be applied to two different styles of asynchronous circuits. The results show that this model has reasonable accuracy on estimated mean delay (2% error on average) compared to detailed analysis carried out with low‐level Monte Carlo (MC) circuit simulations.

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Publication Details

Journal
IET Computers & Digital Techniques
Published
2026-01-01
DOI
https://doi.org/10.1049/cdt2/1529127
Primary Topic
Low-power high-performance VLSI design
Type
article
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article

Statistical Performance Analysis Framework for Bundled‐Data Asynchronous Circuits With Dynamic Voltage Scaling

Maryem Benyoussef, Claude Thibeault, Yvon Savaria
IET Computers & Digital Techniques
Low-power high-performance VLSI design
article

Statistical Performance Analysis Framework for Bundled‐Data Asynchronous Circuits With Dynamic Voltage Scaling

Maryem Benyoussef, Claude Thibeault, Yvon Savaria
article en

Abstract

As the demand for low‐power electronic products grows, asynchronous circuits are considered a good alternative for addressing power consumption issues. Applying dynamic voltage scaling (DVS) in asynchronous circuits can further improve their power efficiency. However, asynchronous circuits face challenges, such as performance analysis considering voltage, temperature, and process variations. This paper proposes a new statistical performance analysis model for asynchronous pipelines. This model can be applied to two different styles of asynchronous circuits. The results show that this model has reasonable accuracy on estimated mean delay (2% error on average) compared to detailed analysis carried out with low‐level Monte Carlo (MC) circuit simulations.

IET Computers & Digital TechniquesVol. 2026(1)
Polytechnique Montréal (CA), École de Technologie Supérieure (CA)
Affordable and clean energy
Openalex Percentile: Top 4%
Low-power high-performance VLSI design
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