High‐Density and Scalable Graphene Hall Sensor Arrays Through Monolithic CMOS Integration

ABSTRACT Electronic devices made from two‐dimensional materials (2DMs) significantly outperform their silicon counterparts; however, silicon CMOS technology remains commercially predominant as it offers the capability to operate dense arrays of devices in a scalable fashion. In particular, graphene Hall sensors (GHSs) offer great improvements in magnetic field sensitivity and resolution compared to silicon Hall‐effect sensors, making them extremely appealing for magnetic field imaging and biosensing. At present, GHS arrays have limited scalability compared to silicon CMOS since they require planar routing for biasing and multiplexing. In this work, we explore strategies to realize high‐density graphene Hall sensor arrays by vertically connecting GHSs with silicon CMOS biasing and multiplexing circuitry, allowing the routing and circuitry to scale with the array. We investigate the importance of design choices in the chip layout and post‐fabrication process in maximizing the reliability of graphene integration onto mm‐scale CMOS dies. Using this integration process, we show that GHSs and CMOS circuits can be monolithically integrated with high yield, creating high‐density magnetic sensing arrays with vertical biasing and readout connections. We expect that these results will lead to further improvements in magnetic sensing technology and broader advancements in large‐scale heterogeneous 2DM‐CMOS systems.