Advances and challenges in Copper–Copper bonding for 3D packaging interconnects

The semiconductor industry faces both opportunities and challenges in the post-Moore era. As artificial intelligence and high–performance computing advance, conventional 2D interconnects have become a performance bottleneck. Three–dimensional integration has thus emerged as a vital solution. Copper is the preferred interconnect material due to its low resistivity, excellent electromigration resistance, and cost–effectiveness. However, conventional thermocompression bonding requires high temperatures, posing thermal damage risks to sensitive devices. This has spurred the development of low–temperature hybrid bonding, which enables direct Cu–Cu and oxide–oxide connections without micro-bumps, permitting closer chip stacking and denser interconnects. This review outlines advancements in Cu–Cu bonding for 3D packaging. It subsequently presents various techniques–including surface pretreatment (e.g., plasma treatment, Chemical Mechanical Polishing (CMP) Process Optimization), hybrid bonding methods (e.g., surface activated bonding), and microstructure control (e.g., preferential (1 1 1) orientation)—that enhance low-temperature bonding performance. Key challenges and corresponding solutions are examined. Finally, the paper summarizes the critical technologies and processes essential for achieving high–quality, low-temperature hybrid bonding. • A comprehensive analysis is presented on surface pretreatment, microstructural control, and multi-process integration for hybrid bonding. • Emphasis is placed on (1 1 1)-oriented nanotwinned copper,which enables high- strength bonding at low temperatures while enhancing interfacial reliability. • This work provides critical technical support for cutting-edge applications such as HBM and AI chips.