Accelet: Hardware-software Co-design of Chiplet-based DNN Accelerators

The rapid growth of deep neural network (DNN) applications has brought unprecedented challenges to the functionality and scalability of accelerators. To address these challenges, the multi-chip-module (MCM) approach facilitates the efficient and cost-effective development of accelerator architectures that can scale from mobile devices to data centers. Chiplet-based systems necessitate a robust platform capable of supporting both hardware modeling and software evaluation, since the performance of the entire system is not only determined by the design of functional units and interconnects, but also strongly affected by the scheduling and mapping of the dataflow. In this paper, we propose Accelet, a comprehensive framework designed to articulate the hardware architecture of chiplet-based accelerators, as well as to investigate the scheduling and mapping strategies for DNN dataflows. Accelet’s versatility in hardware and software modeling empowers the co-design of critical components, including functional units, interconnect topologies, system architectures, and mapping algorithms. Consequently, Accelet can stand as a pivotal tool for the hardware-software co-design of chiplet-based DNN accelerators. Accelet is available at https://github.com/shelljane/accelet-modeling .