FPGA-based dual-channel readout and centroid algorithm for cross-strip anode photon detectors

Crossed-strip anode single-photon detectors have been widely adopted in high-resolution optical imaging systems due to their two-dimensional event localization capability. However, under large-area and high count-rate conditions, conventional readout architectures are limited by bandwidth and processing latency, hindering real-time centroid computation. This study presents an FPGA-based dual-channel signal processing architecture for high-speed centroid extraction in crossed-strip anode detectors. The system integrates an application-specific integrated circuit charge-sensitive preamplifier and a 14-bit analog-to-digital converter to digitize the amplified signals, which are subsequently processed through parallel fast and slow channels. The slow channel performs threshold filtering and trapezoidal shaping for accurate peak extraction, while the fast channel enables event triggering and pileup rejection. Event localization is achieved using a sliding-window approach centered on the peak channel, followed by a symmetric weighted centroid algorithm for spatial coordinate reconstruction. Experimental and simulation results demonstrate that the proposed architecture improves centroid accuracy and processing throughput relative to conventional readout schemes, achieving a stable event rate exceeding 15 MHz and a spatial resolution of 20.16 lp/mm. These results validate the feasibility of the proposed system for real-time, high-resolution photon imaging applications.