Scalability of splitters based on waveguide arrays

Photonic integrated circuits (PICs) are a promising route towards the next generation of classical and quantum information technologies [1, 2]. An important challenge before their widespread implementation is scaling to a competitive footprint and high data transfer rate [3]. This translates into solving the problems of crosstalk between photonic components and energy loss, both exacerbated by minimization. Here, we present the design of a miniature 1:N splitter based on linearly coupled waveguide arrays in silicon on insulator (SOI). Previously, we demonstrated the proof of principle in waveguides realized by femtosecond laser writing in glass [4]. The main difference between these two platforms is the contrast in refractive indices of the waveguide core and cladding. SOI has 2 orders of magnitude higher contrast, which allows for sub-micron interwaveguide spacing while maintaining coupling only between nearest neighbours and single-mode guiding. Our finite-difference-time-domain simulations in Lumerical show promising prospects for realizing small-footprint low-loss splitters. A few-micrometer splitter width requires waveguide fan-out to tens of micrometers needed for coupling to external sources and detectors and, hence, the multiscale simulation. We will discuss these challenges and solutions and offer insights into the mask design as the final step before fabrication. Further developments include incorporating non-nearest-neighbour coupling to achieve the ultimate footprint scaling for single-mode waveguides.