Investigation of backward switching and write margin optimization of SOT-MTJ devices

Spin–orbit-torque magnetic random access memory (SOT-MRAM) offers superior advantages compared to conventional spin-transfer-torque MRAM. However, it suffers from backward switching, which severely constrains the write current window, presenting critical challenges for commercialization. Here, we investigate this phenomenon in full SOT-magnetic tunnel junction structures fabricated on 300 mm wafers. Experiments and numerical simulations demonstrate that Joule heating and field-like torque are the primary factors that dominate the backward switching phenomenon. Based on these insights, the write margin is enhanced by optimizing the SOT layer thickness, pulse width engineering, and stray field optimizations. Our findings establish thermal management as a primary design consideration for scalable SOT-MRAM arrays.