Gate-controlled analog memcapacitance in LaAlO3/SrTiO3 interface-based devices

We demonstrate memcapacitor structures utilizing a quasi-two-dimensional electron gas, formed at the crystalline LaAlO3/SrTiO3 heterointerface, as electrodes and SiO2/SrTiO3 as dielectric layer. The observed memcapacitance originates from charge localization in a lateral floating gate, while an applied gate voltage induces a threshold voltage shift of approximately 1 V and enables reversible tuning of the zero-bias capacitance from ∼147 to ∼386 pF. Furthermore, preprogrammed or erased gate voltages enable controllable shifts of the capacitance hysteresis window toward positive or negative bias, leading to an enlarged capacitance gap of 243 pF compared to the initial value of 100 pF at zero bias. A theoretical model incorporating charge fluctuations within the oxide layer qualitatively reproduces the experimentally observed capacitance hysteresis and its frequency dependence, which is retained up to approximately 1 kHz. The demonstrated low voltage operation (±1 V), combined with gate tunability of oxide interface-based memcapacitors with focus on device physics bridges the path for power-efficient next generation computing architectures.