An In‐Depth Characterization of Page Fault Handling in Modern Persistent Memory Systems

ABSTRACT Recent advancements in Persistent Memory (PM) technologies have enabled the integration of such devices directly into the processor's memory hierarchy, allowing them to be accessed via standard load/store instructions. These developments have revived interest in the design and implementation of systems capable of effectively supporting PM. A prominent approach adopted by several PM programming systems involves leveraging DRAM as a shadow memory to enable the use of modern hardware transactional mechanisms. While this technique offers performance benefits, it presents a critical limitation: when the available DRAM capacity is significantly smaller than that of the PM device, system performance may deteriorate due to excessive paging. Despite its practical implications, this issue remains underexplored in the literature. This article presents, to the best of our knowledge, the first comprehensive performance evaluation of PM systems under constrained DRAM availability. We begin by introducing a user‐level page management framework that underpins our experimental methodology. Subsequently, we conduct a comparative analysis between traditional swap‐based paging mechanisms and more advanced approaches that leverage the redo logs mechanisms of PM systems. Using the TPC‐C suite as a representative benchmark, our experimental results demonstrate that specialized paging strategies can significantly mitigate performance degradation caused by excessive paging. In particular, we observe a decrease in performance loss of up to 3.5× in read‐dominant workloads and up to 2.5× in write‐intensive ones.