A Compendium of Logic Gates Based on Reconfigurable Three‐Independent‐Gate Transistors Realized in FDSOI Hardware

ABSTRACT This work presents the electrical characterization of sixteen different logic gates built entirely from three‐independent‐gate reconfigurable transistors. The circuits are fabricated on full‐scale 300 mm wafers using the industrial 22 nm fully depleted silicon‐on‐insulator process of GlobalFoundries, with only minimal modifications to the baseline CMOS flow. The demonstrations include a reconfigurable 2‐2 AND‐OR‐Inverter gate and a fully functional 1‐bit adder comprising eight transistors. Quasi‐static and transient on‐wafer measurements confirm correct functionality and provide insight into the frequency limitations imposed by the current design and test setup. Finally, to explore scalability, a ripple‐carry adder is simulated based on the experimentally realized 1‐bit adder, illustrating how scaled devices and optimized layouts could enable low‐power, CMOS‐compatible applications.

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Publication Details

Journal
Advanced Electronic Materials
Published
2026-03-23
DOI
https://doi.org/10.1002/aelm.202500782
Primary Topic
Low-power high-performance VLSI design
Type
article
Field-Weighted Citation Impact
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article

A Compendium of Logic Gates Based on Reconfigurable Three‐Independent‐Gate Transistors Realized in FDSOI Hardware

Jens Trommer, A. Zeun, P. Baars, K. Li et al.
Advanced Electronic Materials
Low-power high-performance VLSI design
article

A Compendium of Logic Gates Based on Reconfigurable Three‐Independent‐Gate Transistors Realized in FDSOI Hardware

Jens Trommer, A. Zeun, P. Baars, K. Li, V. Sessi, Juan Martínez, Giulio Galderisi, Binit Syamal, Niladri Bhattacharjee, Fernando Koch, Yuxuan He, T. Mikolajick, Kerstin Poenisch
article en

Abstract

ABSTRACT This work presents the electrical characterization of sixteen different logic gates built entirely from three‐independent‐gate reconfigurable transistors. The circuits are fabricated on full‐scale 300 mm wafers using the industrial 22 nm fully depleted silicon‐on‐insulator process of GlobalFoundries, with only minimal modifications to the baseline CMOS flow. The demonstrations include a reconfigurable 2‐2 AND‐OR‐Inverter gate and a fully functional 1‐bit adder comprising eight transistors. Quasi‐static and transient on‐wafer measurements confirm correct functionality and provide insight into the frequency limitations imposed by the current design and test setup. Finally, to explore scalability, a ripple‐carry adder is simulated based on the experimentally realized 1‐bit adder, illustrating how scaled devices and optimized layouts could enable low‐power, CMOS‐compatible applications.

Advanced Electronic Materials
NaMLab (Germany) (DE), GlobalFoundries (Germany) (DE), Technische Universität Dresden (DE)
Openalex Percentile: Top 11%
Low-power high-performance VLSI design
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