Comprehensive Modeling of Line Edge Roughness and Line Width Roughness in Semiconductor Nanofabrication

Line edge roughness (LER) and line width roughness (LWR) represent critical challenges in semiconductor manufacturing, particularly as technology nodes shrink beyond 5 nm. These stochastic variations in feature dimensions significantly impact device performance, yield, and reliability. This comprehensive research article examines recent advancements in LER/LWR characterization, modeling methodologies, and metrology challenges. We explore spatial characterization parameters that extend beyond basic root mean square (RMS) measurements, including correlation length and roughness exponent, and their relationship to the fractal nature of rough features. The article details implementation approaches for modeling line and surface roughness in virtual fabrication environments, enabling process window optimization without costly experimental iterations. Additionally, we address critical metrology challenges, including measurement bias introduced by image noise and the development of unbiased estimation algorithms. By synthesizing insights from semiconductor manufacturing research, this article provides a foundation for improved LER/LWR control strategies essential for advancing semiconductor technology nodes.