In-SoIC ESD Protection for Chiplet-Based 3D Microsystems: Future Research Directions
Heterogeneous integration opens a pathway to three-dimensional chiplet-based microsystem chips. Electrostatic discharge reliability is a major challenge to future smart chips featuring rich functionalities and ultra performance, utilizing advanced heterogeneous integration and packaging technologies. This paper discusses emerging challenges and future research directions in developing robust electrostatic discharge protection solutions for future systems-on-integrated-chiplets.
Authors
- Runyu Miao (ORCID: https://orcid.org/0009-0005-8980-3233)
- C. Wang
- Xunyu Li (ORCID: https://orcid.org/0009-0001-1737-9796)
- Zijian Yue
Institutions
- University of California, Riverside (US)
Publication Details
- Journal
- Semiconductors and Heterogeneous Integration
- Published
- 2026-03-23
- DOI
- https://doi.org/10.3390/shi1010002
- Primary Topic
- Electrostatic Discharge in Electronics
- Type
- article
- Field-Weighted Citation Impact
- 0.00