Efficient Chip Macro Placement via Discrete Soft Actor-Critic with Enhanced Channel Attention

Macro placement is a critical step in modern IC design, where reinforcement learning (RL) has shown promise by treating it as a sequential decision process. However, existing RL-based methods often suffer from low sample efficiency and insufficient exploration. To address these issues, we propose DSPLACE (Discrete Soft Actor-Critic PLACE), a macro placement approach that integrates Discrete Soft Actor-Critic (DSAC) with Efficient Channel Attention (ECA). DSAC enhances exploration through its maximum-entropy framework, while ECA strengthens state representation by adaptively recalibrating features. Experimental results on ISPD-2005 benchmarks show that DSPLACE improves wirelength by up to 14% and converges about 30.7% faster compared to recent RL-based counterparts.

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Publication Details

Journal
IEICE Transactions on Electronics
Published
2026-01-01
DOI
https://doi.org/10.1587/transele.2025ecs6022
Primary Topic
VLSI and FPGA Design Techniques
Type
article
Field-Weighted Citation Impact
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article

Efficient Chip Macro Placement via Discrete Soft Actor-Critic with Enhanced Channel Attention

Jie Deng, Huan Liu, Lingyan Fan, Guorui FENG et al.
IEICE Transactions on Electronics
VLSI and FPGA Design Techniques
article

Efficient Chip Macro Placement via Discrete Soft Actor-Critic with Enhanced Channel Attention

Jie Deng, Huan Liu, Lingyan Fan, Guorui FENG, Canming DING
article en

Abstract

Macro placement is a critical step in modern IC design, where reinforcement learning (RL) has shown promise by treating it as a sequential decision process. However, existing RL-based methods often suffer from low sample efficiency and insufficient exploration. To address these issues, we propose DSPLACE (Discrete Soft Actor-Critic PLACE), a macro placement approach that integrates Discrete Soft Actor-Critic (DSAC) with Efficient Channel Attention (ECA). DSAC enhances exploration through its maximum-entropy framework, while ECA strengthens state representation by adaptively recalibrating features. Experimental results on ISPD-2005 benchmarks show that DSPLACE improves wirelength by up to 14% and converges about 30.7% faster compared to recent RL-based counterparts.

IEICE Transactions on Electronics
Shanghai University (CN), Hangzhou Dianzi University (CN)
Decent work and economic growth
Openalex Percentile: Top 11%
VLSI and FPGA Design Techniques
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