Development of a Methodology for Characterization the Effect of Local Mismatch of MOSFET Parameters

The paper presents a methodology for characterizing the local mismatch of MOSFET parameters, aimed at increasing the accuracy of the circuit design of modern CMOS ICs. The methodology includes three key stages. At the first stage, specialized test structures are being developed to enable accurate extraction of mismatch values while minimizing parasitic effects and systematic variations associated with the layout. At the second stage, probe measurements of the electrophysical characteristics of the MOSFET pair are expected to be carried out under controlled conditions. At the third stage, the measurement results are subject to statistical processing and further integration into the SPICE model to ensure realistic modeling of parameter mismatch. This paper presents the principles of constructing the methodology and the developed topology of the test structure, which are the basis for subsequent experimental studies and validation of the applicability of the approach.