Temporal Lockstep: Low-Cost Resilient Design for Microcontroller-Class RISC-V Processors

Reliable Cyber-Physical Systems (CPSs) must ensure correct functionality even in the presence of Single Event Transients (SETs) and Single Event Upsets (SEUs) caused by ionizing radiation. Dual-Core Lockstep (DCLS) and Triple-Core Lockstep (TCLS) are common radiation-hardening techniques for processors that rely on spatial redundancy. However, these methods can be prohibitively costly for deeply embedded dependable systems with tight area constraints, such as in automotive applications, where small digital controllers are integral to power electronics, sensors and actuators. We propose a low-cost fault mitigation technique, Temporal Lockstep (TL), which combines temporal redundancy with spatial replication of selected elements to reduce area overhead compared to DCLS and TCLS while providing strong protection against SEUs and SETs. The Power, Performance, and Area (PPA) metrics of the proposed methodology are validated on silicon through a prototype fabricated in TSMC 65nm CMOS technology, featuring a TL-extended RISC-V Ibex processor. The area of the processor is 0.095 mm², consuming 0.92 mW at 0.85V. Additionally, DCLS and TCLS are implemented on the same baseline core for comparison with TL. The area overhead for full pipeline protection is 86%, significantly lower than the 129% and 220% reported for DCLS and TCLS, respectively, on the same core, and representing the lowest-in-class area overhead among state-of-the-art in-pipeline protection schemes. Fault injection simulations show a fault coverage of 99.4% and an average 92% reduction in faulty execution outcomes, demonstrating the effectiveness of the proposed approach.