Performance Analysis of L-Shaped Cladding Layer-Based Dopingless TFET Including Interface Trap Charges and Temperatures
This work investigates the impact of temperature variation and interface trap charges (ITCs) on the DC, RF/analog, and linearity performance of an L-shaped cladding layer-based dopingless TFET (LCD-TFET) using TCAD simulations. Key parameters including band-to-band tunneling (BTBT) rate, transconductance (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g<sub>m</sub></i>), gate capacitance (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C<sub>gg</sub></i>), cut-off frequency (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f<sub>T</sub></i> ), and higher-order nonlinearity metrics are analyzed. Positive interface trap charges (PITC) enhance tunneling efficiency, resulting in improved ON-state current, superior ambipolar suppression, and enhanced RF and linearity performance. The device achieves I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub>/I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> > 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup>, I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub>/I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AMB</sub> > 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup>, and a peak <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f<sub>T</sub></i> of ∼0.12–0.14 THz, whereas negative ITCs degrade these metrics. Temperature variation from 200–500 K mainly affects the subthreshold region due to SRH recombination, while the superthreshold current remains weakly temperature dependent. Elevated temperature improves <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g<sub>m</sub></i>, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f<sub>T</sub></i> , and linearity at low gate bias. Overall, the LCD-TFET demonstrates robust performance under combined thermal and interface trap stress, making it a promising candidate for future low-power and high-frequency applications.
Authors
- Shanidul Hoque
- Rajesh Saha (ORCID: https://orcid.org/0000-0003-2718-7963)
- S. Balakrishnan
- S Shabareeshan
Institutions
- National Institute Of Technology Silchar (IN)
- Vellore Institute of Technology University (IN)
Publication Details
- Journal
- IEEE Access
- Published
- 2026-01-01
- DOI
- https://doi.org/10.1109/access.2026.3676686
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00