Gate-Tunable Planar TiO2/Graphene Memristor for Neuromorphic Computing

This work presents a comprehensive study of planar ITO/TiO2/graphene/polyethylene terephthalate memristive nanostructures for neuromorphic computing applications. We introduce a novel three-terminal memristor device featuring a graphene gate electrode for active control of resistive switching behavior. Through multiphysics modeling using COMSOL Multiphysics, we demonstrate precise control over conductive filament morphology and switching dynamics via gate potential modulation (–5 to +5 V). The developed mathematical model incorporates oxygen vacancy generation, migration, and recombination processes, accurately describing the memristive behavior observed in practical device structures. Parameter variation studies were conducted for TiO2 layer thickness (2–10 nm) and top interelectrode spacing (3–30 nm). Three distinct operational modes were identified: conductance suppression under positive graphene gate potential (1.3–2.6-fold current reduction), filament reorientation under negative gate bias (4–8 orders of magnitude current decrease), and shunting mode at zero gate potential. These findings validate the proposed architecture as a promising platform for energy-efficient neuromorphic systems, artificial intelligence hardware, and in-memory computing applications, potentially enabling significant improvements in neural network computational efficiency. The material combination employed in the memristor structure demonstrates potential for developing transparent and flexible electronics for next-generation computing systems.