Electrode-Modulated oxygen defect profiles in intentionally oxidized chalcogenide ovonic threshold switch selectors

• Intentional oxidation of the chalcogenide active layer for OTS selectors. • Co-optimization of Se/Te composition and intentional oxidation. • Streamlined synthesis of multi-component systems via oxygen incorporation without additional sputtering targets. • Demonstrating the feasibility of high-density integration using a two-terminal via-hole structure. In the push for next-generation memory technologies, crossbar selector devices play a critical role in suppressing sneak-path currents and enabling three-dimensional integration. This study investigates the operation of ovonic threshold switch devices based on Se-alloyed TeO x , focusing on how interfacial oxidation and electrode materials influence the switching behavior. A small amount of oxygen was intentionally incorporated during the deposition step, enabling stable selector operation without the need for additional dopants. Devices fabricated with Pt, W and Cr electrodes exhibited threshold switching with sub-50 ns responses and selectivity exceeding 10 3 , with Pt delivering the best endurance (>10 3 cycles). In contrast, Ti, Ni and Al electrodes formed interfacial oxide layers, as confirmed by cross-sectional transmission electron microscopy, energy-dispersive X-ray spectroscopy, and electron energy loss spectroscopy, leading to resistive random-access memory-like behavior or switching failures. Optimal performance was consistently observed at a specific Se sputtering power (10 W), corresponding to low areal density and improved film uniformity, as verified by X-ray photoelectron spectroscopy, Rutherford backscattering spectrometry, atomic force microscopy, and Raman spectroscopy. These findings demonstrate that selector performance capabilities are governed not only by the active-layer composition but also by electrode-induced interfacial defects. This work offers concrete design guidelines for reliable, low-voltage selector integration in future high-density memory architectures.