Critical Role of Polymer Gate Dielectrics on the Charge Carrier Transport in Perovskite Field‐Effect Transistors

ABSTRACT Understanding the role of interfaces in perovskite devices remains critical for advancing their optoelectronic applications. While most studies on perovskite field‐effect transistors (FETs) focus on bulk or overall film properties, the interface between the semiconductor and dielectric, where the main charge carrier transport occurs, has received relatively limited attention. In this study, polymer films of different dielectric constants were applied to cover hydroxyl groups as trapping sites of a SiO 2 dielectric in 2D phenethylammonium tin iodide‐based FETs. High‐k dielectric polymers with polar functionalities introduce interfacial dipolar disorder that strongly localizes the transported charge carriers, resulting in distinct hysteresis in the device characteristics. On the other hand, low‐k polymers ensure an improved reliability of the device operation with higher charge carrier mobilities. Moreover, the reduced charge localization by the low‐k polymer dielectric surface also contributes to a pronounced bias stress stability being crucial for practical applications. This work provides rational design guidelines for dielectric polymers that promote efficient charge transport and reliable transistor performance, which is also important for the development of flexible electronics.