High Temperature Capable Multilevel Die Interconnect for 600°C operation

Silicon carbide (SiC) electronics have been shown to operate at temperatures exceeding 500°C. GE Research (GE) has demonstrated metal-oxide-semiconductor field-effect transistor (MOSFET)-based SiC analog signal conditioning and digital circuits operational at temperatures >500°C [1, 2] ,and signle NMOS device functionality at 800°C [3]. NASA has demonstrated JFET-based electronics operating above 800°C [3]. Furthermore, the device counts achievable on a single SiC die continues to increase, which results in increased routing complexity. Highly efficient and scalable routing is needed to support the continued advancement in high temperature device densities that is needed to enable future extreme temperature chips. This work will report on the development and characterization of high-temperature multi-level interconnect. Characterization of the interconnect performance across the temperature range from 25-600C will be presented which includes the impact of scaling on interconnect resistance, yield, temperature capability and electromigration performance. An evaluation of further feature size scaling will also be discussed.