Hardware-Based Reduction of Submodule Capacitor Voltage Ripple in Modular MultiLevel Converters: A Critical Review

This paper reviews circuit topologies in the literature that aim to suppress submodule (SM) capacitor-voltage ripple of modular multilevel converters (MMCs), since this low-frequency ripple largely determines the required SM capacitance and thus the overall converter volume, cost, and reliability. The circuit topologies covered in this review include high-frequency (HF) magnetic or switched power channels, transformerless active channel or bridging cells with mid-cell connections, hybrid-MMC and DC-bus management options, SM-level active power decoupling (APD) and active power filters (APF), and structural modifications. Physical power-channel topologies (HF magnetic or switched auxiliary paths) suppress the 2ω capacitor-voltage ripple by transferring the associated low-frequency ripple power to an auxiliary high-frequency path. Hybrid-MMC and direct-current (DC) bus management reduce the required capacitance with only a modest increase in hardware requirements. SM-level APD and APF cells transfer the ripple power into auxiliary storage. Structural and topological arrangements modify the converter architecture itself, leading to architectural simplification, passive attenuation, and a reduced need for measurement or balancing. The reviewed topologies are then compared in terms of ripple reduction, hardware complexity, additional components, cost, and control complexity, and the resulting evidence is synthesised into application-driven design trade-offs and selection guidelines. In addition, DC–DC MMC topologies are discussed separately in a contextual overview.