Low-Noise High-PSRR Capacitor-Less LDO Using Source-Degenerated Folded Cascode OTA for 32-Gbps High-Speed SerDes

In analog/mixed-signal circuit design, achieving low-noise and high-PSRR regulation is vital for high-speed serial links, yet existing LDOs still face major challenges in intrinsic noise suppression and wideband PSRR enhancement. Hence, a novel source-degenerated folded cascode OTA integrated with a voltage subtractor is proposed. Initially, carrier trapping–detrapping at the semiconductor–oxide interface generates intrinsic noise that couples to the regulator output, causing correlated amplitude–phase modulation in sensitive blocks. Thus, a source-degenerated folded cascode OTA with resistive degeneration is introduced to reduce flicker and thermal noise without extra area or power, enabling low-noise, stable regulation that minimizes jitter and improves BER in high-speed SoCs. Additionally, supply-to-gate feedforward through pass device body/well parasitics bypasses the error amplifier, causing high-frequency supply noise coupling that leads to PSIJ in multi-phase clock trees. So, a voltage subtractor high-PSRR topology is introduced, which cancels supply noise at the pass device gate, boosting wideband PSRR without bulk capacitors, thereby reducing PSIJ and enhancing eye diagram and BER in high-speed SoCs. Experimental results confirm that the proposed model performs better, reducing intrinsic noise by [Formula: see text]50%, improving wideband PSRR from [Formula: see text]7.3[Formula: see text]dB to [Formula: see text]60[Formula: see text]dB at 10[Formula: see text]KHz, and enhancing jitter tolerance and BER with cleaner eye margins in high-speed SerDes links.