Modeling Glitches due to Multiple Input Switching using Machine Learning

Timing models in conventional technology libraries assume that only one input pin switches during a transition, while all side inputs are held to constant values. This assumption neglects the significant impact of multiple-input switching (MIS), which becomes increasingly relevant at advanced process nodes due to higher clock frequencies. The MIS can lead to two critical problems: delay variations and glitches at the output pin. In this paper, we focus on addressing the problem of MIS-induced glitches, and to tackle this challenge, we propose an artificial neural network (ANN)-based model to predict the characteristics of these glitches. We demonstrate that the characteristics of glitches, such as their height and area, depend on the capacitive load, transition time at the inputs, and the temporal distance between signals at the inputs. Subsequently, we develop a methodology to generate and optimize a comprehensive dataset using these features, which is then utilized to develop the proposed model, minimizing computational costs while ensuring thorough glitch characterization. To minimize the number of SPICE simulations required for generating training datasets of complex logic gates, we formulate the identification of glitch-prone MIS transitions as a satisfiability (SAT) problem and employ a SAT solver to efficiently prune the search space. Using an ISCAS benchmark circuit, we demonstrate that these predictions from the proposed model are reasonably accurate (average RRMSE 3.44% and maximum RRMSE of 5.51% compared to reference SPICE simulations). Also, the proposed model offers ∼ 10, 000 × times improvement during inference over conventional SPICE computations. The existing timing libraries augmented with the proposed model thus can be utilized in design optimization. We also illustrate the use of the proposed model in glitch attenuation algorithms for design transformations’ evaluation. Furthermore, the signal integrity and noise analysis tools can also employ the proposed glitch prediction model, as demonstrated in this paper.