An Energy- and Endurance-Aware Hybrid CMOS–SDC Memristor Convolutional Spiking Neural Network for Edge Intelligence

The inherent bottleneck of the von Neumann architecture and the limited power budget of edge devices necessitate energy-efficient hardware solutions for artificial intelligence. Memristor-based In-Memory Computing (IMC) has emerged as a promising candidate; however, the high-power consumption of peripheral circuits, particularly Analog-to-Digital Converters (ADCs), and the reliability issues of memristive devices remain significant challenges. In this paper, we propose a hybrid Convolutional Spiking Neural Network (CSNN) architecture designed for resource-constrained edge computing. Our approach integrates digital Non-Leaky Integrate-and-Fire (NLIF) neurons with Knowm Self-Directed Channel (SDC) memristor-based synapses in a 1T1R crossbar array. To maximize power efficiency, we replace conventional high-resolution ADCs with a streamlined readout circuit utilizing a Current Sense Amplifier (CSA) and a 1-bit comparator. Furthermore, we employ an intensity-to-latency temporal coding scheme to minimize spike activity and mitigate device endurance degradation. We validated the proposed system using the MNIST dataset, achieving a classification accuracy of 97.8%, which is comparable to state-of-the-art floating-point SNNs using supervised learning methods. Power analysis confirms that our 1-bit readout method consumes only 18.4% of the energy required by an 8-bit ADC-based approach while maintaining negligible accuracy loss. Additionally, the deterministic single-spike nature of our temporal coding significantly reduces write stress on memristors compared to rate coding. These results demonstrate that the proposed hybrid CSNN offers a robust and energy-efficient solution for neuromorphic edge intelligence.