Stability and Synchronisation of MMC-HVDC Systems Using SRF and Inertia-based PLLs

Phase-Locked Loops (PLLs) are critical for synchronising Modular Multilevel Converter High Voltage Direct Current (MMC-HVDC) systems with Alternating Current (AC) grids, yet their stability impacts remain underexplored. This study systematically compares the impacts of the Synchronous Reference Frame-PLL (SRF-PLL) and the Inertia PLL (IPLL) on small-signal stability and large-signal synchronisation. A unified framework is adopted to enable unbiased comparison by aligning their bandwidths. A small-signal model, incorporating PLL dynamics, is developed, based on which PLL impacts are examined using impedance-based generalized Nyquist criteria. The analysis results show that system stability depends primarily on PLL bandwidth rather than structure. This reveals inherent limitations of PLL-based synchronisation and motivates PLL-less designs for improving stability. To enhance large-signal synchronisation, a phase correction pathway is introduced for the SRF-PLL. This approach improves synchronisation while avoiding steady-state phase detection errors inherent to the IPLL. Finally, all results are verified by non-linear time-domain electromagnetic transient simulations in PSCAD. This work advances quantitative understanding of PLL characteristics and stability impacts in MMC-HVDC systems, providing motivation for adopting PLL-less system designs.