Re-Decode: A General-Purpose CPU architecture model for extensive FU usage

In the nature of current CPU architectures, the full utilization of the Functional Units (FUs) is not always accomplished, generating a negative impact on Instructions per Cycle (IPC). In order to get the best performance out of the FUs, the Re-Decode algorithm is implemented as an architectural model in the Gem5 architectural simulator; this model redirects the instructions in queue into similar instructions, mainly scalar or vector instructions, that will take advantage of unused FUs slots without changing the final result of the program. This architectural model takes advantage of the instructions affinity, defined as the capability of some instructions to obtain the same result value; the instructions with high affinity are pairs of General-Purpose operations and their respective Scalar operation for vector registers, as well as the Scalar operations with their respective Vector operations, meaning that regardless of being a General-Purpose Register (GPR) or a vector register with a Scalar value, the result of their execution will always be the same for an independent set of input values. This aims to distribute the instructions more efficiently between every FU, concluding with a higher IPC. The Re-Decode architectural model was able to increase up to 9% the IPC on a threaded workflow and reduce the number of instructions waiting for an FU by a factor of 52 times by being Re-Decoded.