A Survey of FPGA Placement Algorithms: From Monolithic Devices to Multi-Die Architectures

Monolithic integration of large FPGA-dies increasingly encounters physical and economic constraints. Fully integrated 3D FPGAs remain commercially unavailable. Hence, interposer-based multi-die solutions (often referred to as 2.5D FPGAs) have emerged as a practical and scalable alternative. These architectures offer higher integration density, improved yield, and enhanced performance scalability by circumventing limitations imposed by reticle size and the complexities of manufacturing large monolithic dies. Interposers facilitate high-bandwidth, low-latency communication between multiple FPGA-dies within a single package, making them a promising bridge technology. However, distributing an FPGA design across multiple dies makes placement and routing challenging. While general FPGA placement has been the subject of various surveys, no existing work focuses specifically on the unique challenges, design considerations, and state-of-the-art techniques associated with placement in 2.5D multi-die FPGAs. This survey aims to fill that gap and provide insights into this rapidly evolving field.