Development and Performance Analysis of 8T SRAM Cell at 14 nm FinFET Technology

The tremendous advancements in the electronics sector, from advanced transistors to the 5G services that are in use now provides an idea of the incredible developments in this sector in recent times. The semiconductor devices play a significant role in the design of primary memory cells like Static Random Access Memory (SRAM). SRAM cells are an integral part of this new generation of VLSI technology, but they become predictive while trying to execute them with nodes. The in-competence of MOSFETs in the nano regime led inevitably to the use of FinFET technology in which the number of fins can be increased while scaling the transistor sizes thereby increasing the transistor performance. There are other major advantages like power reduction and lesser area to the SRAMs based on FinFETs. The variations in its process have a major impact on the threshold voltage, Effective Oxide Thickness, off-state current, drain current and Subthreshold Swing. SRAMs utilizing 14 nm Bulk-FinFET are developed here with different observations like access time of two 8T SRAM cells, thermal stability and noise ratio. The analysis of the reduction in percentage of errors while operating and relying on the stability of the SRAM cell is performed using Cadence tools. When compared to Planar transistors based SRAM, the soft error rate in FinFET SRAM is considerably dropped as shown by TCAD simulations. The results from various simulations show that if we increase the PD transistor fins and with reduced power supply the Reverse Static Noise Margin can be obtained.