Fault Modeling and Testing of Spin-Orbit Torque-Based Multipillar Memory Cell

Multipillar spintronic memory has emerged as a promising candidate for next-generation magnetoresistive random access memory (MRAM), offering advantages such as low power consumption, high integration density, and suitability for in-memory computing and neuromorphic applications. However, the intricate fabrication of multipillar structures increases susceptibility to manufacturing defects, necessitating robust and efficient testing methodologies. In this work, we analyze a singlecell spin-orbit torque (SOT)-based multipillar MRAM device under various resistive bridges, open defects, and transistor stuck-on/stuck-open faults. Corresponding fault models such as stuck-at faults (SAFs), transition faults (TFs), coupling faults (CFs), and read disturbance faults (RDFs) are proposed. A dedicated test algorithm is developed to detect these faults using a multilevel sensing scheme. It offers full coverage of all SAFs, TFs, CFs, and RDFs, and enables concurrent testing of multiple MTJs to significantly reduce test time. The proposed approach provides a robust design for testing framework for emerging multilevel SOT-MRAM architectures.

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Publication Details

Published
2025-10-12
DOI
https://doi.org/10.1109/vlsi-soc64688.2025.11421751
Primary Topic
Semiconductor materials and devices
Type
article
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article

Fault Modeling and Testing of Spin-Orbit Torque-Based Multipillar Memory Cell

Lorena Anghel, Grégory Di Pendina, Arshid Nisar
Semiconductor materials and devices
article

Fault Modeling and Testing of Spin-Orbit Torque-Based Multipillar Memory Cell

Lorena Anghel, Grégory Di Pendina, Arshid Nisar
article en

Abstract

Multipillar spintronic memory has emerged as a promising candidate for next-generation magnetoresistive random access memory (MRAM), offering advantages such as low power consumption, high integration density, and suitability for in-memory computing and neuromorphic applications. However, the intricate fabrication of multipillar structures increases susceptibility to manufacturing defects, necessitating robust and efficient testing methodologies. In this work, we analyze a singlecell spin-orbit torque (SOT)-based multipillar MRAM device under various resistive bridges, open defects, and transistor stuck-on/stuck-open faults. Corresponding fault models such as stuck-at faults (SAFs), transition faults (TFs), coupling faults (CFs), and read disturbance faults (RDFs) are proposed. A dedicated test algorithm is developed to detect these faults using a multilevel sensing scheme. It offers full coverage of all SAFs, TFs, CFs, and RDFs, and enables concurrent testing of multiple MTJs to significantly reduce test time. The proposed approach provides a robust design for testing framework for emerging multilevel SOT-MRAM architectures.

Centre National de la Recherche Scientifique (FR), Commissariat à l'Énergie Atomique et aux Énergies Alternatives (FR), CEA Grenoble (FR), Spintronique et Technologie des Composants (FR), Université Grenoble Alpes (FR)
Affordable and clean energy
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Semiconductor materials and devices
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Fault Modeling and Testing of Spin-Orbit Torque-Based Multipillar Memory Cell — Lorena Anghel, Grégory Di Pendina, et al. · (2025) | TGRS Research Map | TGRS